A PLL circuit is well-known as a frequency converter circuit. This PLL circuit includes a frequency divider (pre-scaler) for reducing the frequency of a reference clock signal or a local oscillation (Lo) signal to a control frequency. This PLL circuit needs to be measured and checked in a development stage or at the time of mass production or shipping. The PLL circuit may frequently be enclosed within the semiconductor integrated circuit device. In measuring the PLL circuit, it is practiced to supply a signal of the frequency and the power, desired to be used for evaluation, from the outside equipment to the frequency divider, in a manner free from the influence of self-oscillations of the voltage controlled oscillator (VCO), and to monitor the frequency of the output signal to measure the input sensitivity.
FIG. 3 depicts a block diagram showing an illustrative constitution of a conventional semiconductor integrated circuit device. Referring to FIG. 3, a PLL circuit is constituted during the normal operation by a feedback loop composed of a voltage controlled oscillator V100, a buffer B100, a frequency divider PS, a phase comparator PC and a charging pump CP. The oscillation frequency of the voltage controlled oscillator V100 is controlled so that the output signal of the frequency divider PS will be in phase with a signal at a reference signal input terminal S1.
The input terminals of the voltage controlled oscillator V100, such as base terminals, not shown, supplied with positively fed back outputs of a differential amplifier that makes up the voltage controlled oscillator, are derived to outside as input terminals IN11 and IN12 via capacitors C11, C12. In testing, an RF test signal TS is supplied from a signal generator to the input terminals IN11 and IN12 via balun T100. The power and the frequency of the RF test signal TS are subjected to sweeping at this time to test the input sensitivity.
The voltage controlled oscillator V100 normally includes an enclosed tank circuit. If, in particular, there is not provided a mode for controlling the voltage controlled oscillator V100, the voltage controlled oscillator begins oscillating at the same time as the power supply is connected in circuit. Hence, a signal of the voltage controlled oscillator V100 in the self-running state is supplied to the frequency divider PS being tested. It is however possible to control the power and the frequency of the output signal of the voltage controlled oscillator V100, by e.g., an external signal generator, a signal of a magnitude sufficient to control the self-oscillations of the voltage controlled oscillator V100 is supplied to the input terminals IN11, IN12. This controlled signal may be supplied to the frequency divider PS to measure an output and hence the input sensitivity.